1. Field of the Invention
The invention relates to a semiconductor device, in particular, an ESD protection element including a MOS transistor having a high ESD protection characteristic.
2. Description of the Related Art
An LDMOS transistor as well as IGBT has higher switching performance and more stable performance than a bipolar type power transistor, and thus it is widely used in an inverter circuit for a switching power supply such as a DC-DC converter, an inverter circuit for a motor or a lighting device, and so on. The LDMOS is an abbreviation of a Lateral Double Diffused Metal Oxide Semiconductor and means a lateral double-diffused gate MOS. The ESD is an abbreviation of Electro-Static Discharge and means the discharge of static electricity.
Conventionally, for addressing ESD, various types of semiconductor devices including protection circuits using semiconductor devices have been proposed. Typically, as shown in FIG. 8, an internal circuit 56 is protected by connecting a PN junction diode 52 between an input output terminal 50 and a power supply line 51, connecting a PN junction diode 54 between the input output terminal 50 and a ground line 53, and connecting a PN junction diode 55 between the power supply line 51 and the ground line 53.
However, as the miniaturization of elements is enhanced for a demand for higher speed and so on, the electrostatic breakdown tolerance of a semiconductor device is decreased and thus a more proper ESD protection element is essential. When an LDMOS transistor is used as a power transistor as an ESD protected element, a MOS transistor may be used as an ESD protection element for the reason that the snapback characteristic of its parasitic bipolar transistor which will be described below is usable or the like.
FIG. 7 shows an example of a system including a drive circuit 36 and two power NLDMOS transistors 30 and 31 as ESD protected elements connected in series, the system being disposed between a power supply 34 and a ground line. As ESD protection elements, MOS transistors 32 and 33 are connected in series in each of which the source electrode and the gate electrode are connected, being disposed between the power supply 34 and the ground line as shown in FIG. 7.
The connection node of the NLDMOS transistors 30 and 31 and the connection node of the ESD protection elements 32 and 33 are connected to each other, being led to an output terminal 35. In this system, the snapback voltages Vt1 of the MOS transistors 32 and 33 as the ESD protection elements are designed to be smaller than the snapback voltages VT1 of the power NLDMOS transistors 30 and 31 as the ESD protected elements.
By this, when a surge voltage by large positive static electricity is applied to the drain electrode, the surge current is discharged from the MOS transistor 32 or 33 on the ESD protection element side and the power NLDMOS transistors 30 and 31 as the ESD protected elements are protected.
Although details will be described below, the snapback voltage means a trigger voltage to start discharging static electricity to a ground line or the like when a surge voltage by large static electricity is applied to an input output terminal or the like. Japanese Patent Application publication No. 6-177328 discloses the enhancement of the ESD protection characteristic by decreasing the snapback voltage when a MOS transistor is used as an ESD protection element.
Ordinarily, in a power NLDMOS transistor as an ESD protected element, the P+ type contact layer is formed in parallel with the N+ type source layer, and the potential of the P type body layer as the back gate is fixed to the potential of the N+ type source layer. As a result, even when holes generated by an avalanche breakdown near the N+ type drain layer flow into the N+ type source layer side, the holes are absorbed in the P+ type contact layer and the potential of the P type body layer is not increased largely, thereby preventing the turn-on of the parasitic bipolar transistor which uses the N+ type source layer as the emitter, the P type body layer as the base and the N+ type drain layer as the collector.
On the other hand, as described below, a MOS transistor as an ESD protection element uses the phenomenon that holes, which are generated near the N+ type drain layer by an avalanche breakdown and flow into the N+ type source layer side when a surge voltage by positive static electricity larger than the drain-source breakdown voltage BVDS is applied to the drain electrode, increase the potential of the P type body layer to a predetermined value or more to turn on the parasitic bipolar transistor described above.
Therefore, the P+ type contact layer need to have a structure which does not easily absorb holes accumulated in the P type body layer around the N+ type source layer, or need to be disposed away from the N+ type source layer. This structure enables the parasitic bipolar transistor of the ESD protection element to turn on and discharge static electricity to the ground line etc through the ESD protection element. As a result, the ESD protected element is protected from a surge voltage by positive static electricity.
In the ESD protection element, the P+ type contact layer functions as a discharge path of static electricity when large negative static electricity is applied to the drain electrode. Therefore, it is not necessary to dispose the P+ type contact layer in parallel with the N+ type source layer, and the P+ type contact layer is disposed so as to surround the peripheral region of the MOS transistor including the drain region disposed away from the N+ type source layer.
By disposing the P+ type contact layer so as to surround the peripheral region of the MOS transistor as the protection element, the holes described above do not easily flow into the P+ type contact layer and are accumulated in the P type body layer near the N+ type source layer, thereby increasing the potential of the P type body layer. Therefore, the parasitic bipolar transistor described above turns on and discharges a surge current by positive static electricity to the ground line etc immediately.
However, in a case of an ESD protection element using finger form electrodes in which a plurality of finger form source electrodes and a plurality of finger form drain electrodes are inserted therebetween, a parasitic bipolar transistor does not turn on in the finger portion in the peripheral region of the MOS transistor near the P+ type contact layer and the ESD protection element may not work enough.
This is because a parasitic bipolar transistor formed by an N+ type source layer, a P type body layer and an N+ type drain layer disposed nearer the P+ type contact layer in the peripheral region turns on less easily, since holes flowing into the N+ type source layer easily flow into the P+ type contact layer.
It is necessary to realize an ESD protection element in which even a parasitic bipolar transistor formed by an N+ type source layer, a P type body layer and an N+ type drain layer in the finger portion near the P+ type contact layer surrounding the peripheral region of the MOS transistor turns on enough.